3D-stacked chip cubes include vertically stacked multiple chips in a package to achieve chip assemblies with higher density as revealed in U.S. Pat. Nos. 6,448,661, 7,151,009, and 6,916,725. The existing processes are to singulate the chips from wafers first, then vertically stack multiple chips, then followed by package-level electrical testing. However, the pitch of the external micro terminals of the 3D-stacked chip cubes is much smaller than the pitch of conventional semiconductor packages such as smaller than 100 μm which can not be tested by conventional package-level testing tooling and testers for electrical test.
An interposer to test 3D-stacked chip cubes was proposed where 3D-stacked chip cubes were soldering onto an interposer to realize a temporary bonding firstly and followed by electrical testing by package probing at larger-pitch terminals on the interposer. However, the extra cost of an interposer plus the testing cost will be high and the testing results will not be accurate enough due to the interference of the interposer.
Moreover, another electrical testing method was proposed where 3D-stacked chip cubes were disposed on carrier wafers with adhesive to simulate un-singulated chips integrated on a wafer so that 3D-stacked chip cubes could be loaded into a wafer tester to perform wafer-level testing to meet the fine pitch requirements of chip probing. However, “overkill” would be encountered due to disposing tolerance of 3D-stacked chip cubes and the shifting of adhesive which can not align with the probes of a probe cards during chip probing, i.e., some “OK” 3D-stacked chip cubes will be judged as “NG”. The only way to overcome “overkill” issues is to frequently stop wafer testers to debug, repair, and maintenance to correct probe card misalignment issues leading to poor testing efficiency and lower productivity.